A fiber optic communications link typically includes a transmitter which transmits and directs light emitted from a laser diode through a fiber optic cable. At the receiving end of the fiber optic cable the light is detected by a photo detector and converted into an electrical current. The current is converted to voltage by a transimpedance amplifier and then amplified by a limiting amplifier. The amplified voltage signal is applied to a clock and data recovery (CDR) circuit which extracts a clock signal from the received data (e.g., NRZ data). The CDR compares the frequency of the clock signal to frequency of data signal and adjusts the frequency of the clock signal to equal the frequency of the data signal to achieve a frequency lock (acquisition). The clock and data recovery circuit also acquires and tracks the phase of the incoming data, which is known as phase acquisition.
The CDR circuit typically utilizes a frequency lock loop (FLL) for frequency acquisition and a phase lock loop (PLL) circuit for phase acquisition. The FLL typically includes a frequency detector, a charge pump, a loop filter, a voltage controlled oscillator (VCO) and a digital divider. The PLL circuit typically includes the same components as the FLL, but utilizes a phase detector instead of a frequency detector.
The frequency detector of the FLL is typically implemented with two distinct devices which include a coarse frequency detector (CFD) and a fine frequency detector. The function of the CFD is to adjust the frequency of the clock signal so that it is close to the frequency of the incoming data signal, e.g., the frequency of clock signal is within about 10% of the frequency of the data signal. Then the fine frequency detector takes over and adjusts the frequency of the clock signal so that it is very close, e.g., within about 500 ppm, of the frequency of the data signal.
A typical CFD compares the frequency of the clock signal to the frequency of the data signal and produces a frequency up-pulse when the frequency of the clock signal is less than the frequency of the data signal. The CFD continues comparing the frequency of the clock signal to the frequency of the data signal until the frequency of clock signal is close to the frequency of the data signal. The frequency up-pulse is applied to a charge pump which generates a current up-pulse. The current up-pulse is applied to a loop filter which applies an increase in the voltage to the VCO. The VCO then increases its output frequency proportional to the amount of voltage applied to it, known as the frequency step size.
Conventional CFDs do not control the width of the frequency up-pulses generated by the CFD and as a result often produce up-pulses with very small pulse widths especially when the frequency of the clock signal approaches the frequency of the data signal. The result is that frequency step size is often very small which means the frequency of the clock signal is increased in very small increments which increases the frequency acquisition time. A single narrow frequency up-pulse applied to the charge pump results in a change as small as about 10 ppm (e.g., 0.001%) in the VCO frequency. Moreover, up-pulses with very narrow pulse widths require a more complex and high speed charge pump.
Moreover, conventional CFDs are designed to detect both the rising and falling transitions of a single positive or negative pulse in the data signal. A conventional CFD compares the width of a single pulse in the data signal to a single clock period to determine if the frequency of the clock signal is less than the frequency of the data signal. However, because the data signal is typically transmitted by a laser, the 1's can be narrower than the 0's. The result is that conventional CFDs are susceptible to bimodal jitter (BMJ). BMJ arises when one edge of the data sees a different delay than the other edge and has the effect of making a single pulse narrower than it should be. Because conventional CFDs are comparing both the rising and the falling transition of a single pulse of the data signal, when the falling edge of the data occurs too fast, e.g., in the case of a transmitted 1, BMJ has the effect of making the data appear at a higher frequency than it actually is which results in a large residual frequency error.
Conventional CFDs also typically employ at least four parallel circuits (slices) which each includes at least two storage devices, e.g., flip-flops. The clock signal is divided (typically by 2) to generate two reset signals which are stored in the two storage devices. The two reset signals act as windows to be compared to the incoming data signal. If a single positive or negative pulse exists within either of the two reset windows, then the frequency of the clock is slow and the CFD generates an up-pulse to increase the frequency of the clock.
The result, as discussed above, is that conventional CFDs rely on detecting both positive and negative transitions of each positive and negative pulse in the data signal which results in BMJ and large residual frequency error. Moreover, the design of conventional CFDs is complex, requiring both storage devices to have three inputs for the data, clock and reset signals. Employing three inputs on both storage devices is difficult to implement at high frequencies. An example of one such prior art CFD is disclosed in “The Design and Implementation of a New Wide Range Frequency Detector” by Steve S. Paik, MEEE Report, MIT, July 1998, incorporated by reference herein.